This invention relates to scheduling in cases where physical resources on a physical computer are logically partitioned to generate a plurality of logical partitions (hereinafter referred to as LPARs) and to allow for the sharing of a plurality of physical CPUs among a plurality of logical CPUs by time division.
In recent years, the improved performance per physical computer has made popular a method involving building a plurality of logical computers on a physical computer, in order to cut management cost and power consumption by increasing the rate of computer integration. Logical computers can be built by, for example, a method in which a hypervisor generates and controls at least one logical computer by allocating divided or shared computer resources such as a physical CPU, a physical memory, and an input/output apparatus to logical partitions (LPARs), which are logical computers.
In order to share one physical CPU among a plurality of LPARs, a hypervisor needs to execute time division in which the physical CPU is divided into unit times called time slices, and to manage the running times of logical CPUs allocated to the respective LPARs during sharing. This control is generally called scheduling.
A non-uniform memory access (NUMA) configuration, on the other hand, is a computer configuration in which a plurality of CPUs and a memory on a physical computer are grouped into one group called a node, and an access cost that is required of a physical CPU to access a memory in the same node as the physical CPU is smaller than an access cost that is required of the physical CPU to access a memory in another node. The memory in the same node is called a local memory and the memory in another node is called a remote memory.
When many physical CPUs are installed, the NUMA configuration, where nodes can separately access physical memories in parallel, is reduced in conflicts among physical CPUs with regards to physical memory access, whereas a uniform memory access (UMA) configuration, where the same memory access cost is required of every physical CPU to access a physical memory, has a high chance of conflict. Because of this advantage, the NUMA configuration is employed by not a small number of computers in recent years, where the number of CPUs installed has increased.
One of mechanisms for reducing the cost of accessing a physical memory is a physical memory cache (hereinafter referred to as cache) that is located physically close to physical CPUs to save the contents of the memory temporarily. Each time the physical memory is accessed, the accessed contents of the memory are saved in the cache so that, the next time, the same contents of the memory can be accessed by accessing the cache. The cost of accessing the physical memory is reduced as a result. Generally speaking, access to a cache is quicker than access to a local memory.
In JP 2008-186136 A, there is disclosed a technology of a virtual computer installation method in which, when a system is busy throughout, high-priority processing is distributed among physical CPUs to be executed while the processing performance of LPARs is kept from dropping.